Complementary metal-oxide-semiconductor (CMOS) technologies integrate P- and N-channel field effect transistors (FETs) to form an integrated circuit on a single semiconductor substrate. Latch-up, which is precipitated by unwanted transistor action of parasitic bipolar transistors inherently present in bulk CMOS devices, may be a significant issue for bulk CMOS technologies. The unwanted parasitic transistor action, which has various triggers, may cause failure of bulk CMOS devices. For space-based applications, latch-up may be induced by the impingement of high energy ionizing radiation and particles (e.g., cosmic rays, neutrons, protons, alpha particles). Because the integrated circuit cannot be easily replaced in space flight systems, the chip failure may prove catastrophic. Hence, designing bulk CMOS devices with a high tolerance to latch-up is an important consideration for circuit operation in the natural space radiation environment, as well as military systems and high reliability commercial applications.
Bulk CMOS device designs may be adjusted to increase latch-up immunity. For example, latch-up immunity may be increased in 0.25 micron device technologies by building bulk CMOS devices on epitaxial substrates (e.g., a p-type epitaxial layer on a highly-doped p-type substrate wafer). Highly-doped substrate wafers provide excellent current sinks for currents that, if unabated, may initiate latch-up. However, epitaxial substrates are expensive to produce and may increase the design complexity of several critical circuits, such as electrostatic discharge (ESD) protective devices.
Guard ring diffusions represent another conventional approach for suppressing latch-up. However, guard ring diffusions are costly because they occupy a significant amount of active area silicon real estate. In addition, although guard ring diffusions collect a majority of the minority carriers in the substrate, a significant fraction may escape collection underneath the guard ring diffusion.
Semiconductor-on-insulator (SOI) substrates are recognized by the semiconductor community as generally free of latch-up. However, CMOS devices are expensive to fabricate on an SOI substrate, as compared to a bulk substrate. Furthermore, SOI substrates suffer from various other radiation-induced failure mechanisms aside from latch-up. Another disadvantage is that SOI devices do not generally come with a suite of ASIC books that would enable simple assembly of low-cost designs.
Conventional CMOS devices are susceptible to latch-up generally because of the close proximity of N-channel and P-channel devices. For example, a typical CMOS device fabricated on a p-type substrate includes a P-channel transistor fabricated in an N-well and an N-channel transistor fabricated in a P-well. The opposite conductivity N- and P-wells are separated by only a short distance and adjoin across a well junction. This densely-packed bulk CMOS structure inherently forms a parasitic lateral bipolar (PNP) structure and parasitic vertical bipolar (NPN) structure. Latch-up may occur due to regenerative feedback between these PNP and NPN structures.
With reference to FIG. 1, a portion of a standard triple-well bulk CMOS structure 30 (i.e., CMOS inverter) includes a P-channel transistor 10 formed in an N-well 12 of a substrate 11, an N-channel transistor 14 formed in a P-well 16 of the substrate 11 that overlies a buried N-band 18, and a shallow trench isolation (STI) region 20 separating the N-well 12 from the P-well 16. Other STI regions 21 are distributed across the substrate 11. The N-channel transistor 14 includes n-type diffusions representing a source 24 and a drain 25. The P-channel transistor 10 has p-type diffusions representing a source 27 and a drain 28. The N-well 12 is electrically coupled by a contact 19 with the standard power supply voltage (Vdd) and the P-well 16 is electrically coupled by a contact 17 to the substrate ground potential. The input of the CMOS structure 30 is connected to a gate 13 of the P-channel transistor 10 and to a gate 15 of the N-channel transistor 14. The output of CMOS structure 30 is connected to the drain 28 of the P-channel transistor 10 and the drain 25 of the N-channel transistor 14. The source 27 of the P-channel transistor 10 is connected to Vdd and the source 24 of the N-channel transistor 14 is coupled to ground. Guard ring diffusions 34, 36 encircle the CMOS structure 30.
The n-type diffusions constituting the source 24 and drain 25 of the N-channel transistor 14, the isolated P-well 16, and the underlying N-band 18 constitute the emitter, base, and collector, respectively, of a vertical parasitic NPN structure 22. The p-type diffusions constituting the source 27 and drain 28 of the P-channel transistor 10, the N-well 12, and the isolated P-well 16 constitute the emitter, base, and collector, respectively, of a lateral parasitic PNP structure 26. Because the N-band 18 constituting the collector of the NPN structure 22 and the N-well 12 constituting the base of the PNP structure 26 are shared and the P-well 16 constitutes the base of the NPN structure 22 and also the collector of the PNP structure 26, the parasitic NPN and PNP structures 22, 26 are wired to result in a positive feedback configuration.
A disturbance, such as impinging ionizing radiation, a voltage overshoot on the source 27 of the P-channel transistor 10, or a voltage undershoot on the source 24 of the N-channel transistor 14, may result in the onset of regenerative action. This results in negative differential resistance behavior and, eventually, latch-up of the bulk CMOS structure 30. In latch-up, an extremely low-impedance path is formed between emitters of the vertical parasitic NPN structure 22 and the lateral parasitic PNP structure 26, as a result of the bipolar bases being flooded with carriers. The low-impedance state may precipitate catastrophic failure of that portion of the integrated circuit. The latched state may only be exited by removal of, or drastic lowering of, the power supply voltage below the holding voltage. Unfortunately, irreversible damage to the integrated circuit may occur almost instantaneously with the onset of the disturbance so that any reaction to exit the latched state is belated.
What is needed, therefore, is a semiconductor structure and fabrication method for modifying standard bulk CMOS device designs that suppresses latch-up, while being cost effective to integrate into the process flow, and that overcomes the disadvantages of conventional bulk CMOS semiconductor structures and methods of manufacturing such bulk CMOS semiconductor structures.